http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S62200776-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_930d026de3a6f8109fa00a85852fe8e4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B41J2-455 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B41J2-45 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G03G15-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B41J2-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-64 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-62 |
| filingDate | 1986-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae6139511b30efbef1f448550b9cf587 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e9617524c9730d944152a98a322655ce http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f4e1cdf72716d55b602023a9e236ffa3 |
| publicationDate | 1987-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S62200776-A |
| titleOfInvention | Substrate for light-emitting diode array |
| abstract | PURPOSE: To obtain a substrate costing low and still having excellent heat dissipating properties, by utilizing an aluminum substrate whose surface is alumetized. n CONSTITUTION: An aluminum substrate 1, which carries a light-emitting diode array 9 thereon and on which a circuit for driving the light-emitting diode array 9 is patterned, has a surface alumetized. For example, an alumetized aluminum layer 2 may be formed in the aluminum substrate 1 by anodic oxidation. A conductor layer 3 is formed on this substrate 1 by a thin-film forming technique such as spattering, vapor deposition or the like. A gold deposit layer 8 is provided thereon, and a light-emitting diode array 9 of GaAsP or the like is disposed and fixed on the layer 8 by the die bonding or by the use of a conducting adhesive or the like. A wiring pattern consisting of a gold deposit layer 8, a resistance layer 4, an insulation layer 5, a conductor layer 7 and a protection layer 7 is formed in the region on the conductor layer 3 not covered with the first mentioned gold deposit layer 8, and the wiring pattern is connected to the light-emitting diode array 9 by wire bonding. n COPYRIGHT: (C)1987,JPO&Japio |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101037325-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6995405-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100703218-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013082099-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-02086972-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008211221-A |
| priorityDate | 1986-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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