http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S62101044-A

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filingDate 1985-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b58676762e9f8c0c92f0481a67867af9
publicationDate 1987-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-S62101044-A
titleOfInvention Manufacture of hybrid integrated circuit device
abstract PURPOSE: To improve the yield of a hybrid integrated circuit having high reliability and high heat resistance, and to reduce cost thereof by aging a chip part on a substrate under clean environment prior to hermetic seal and repairing or exchanging defectives on the basis of electric function inspection. n CONSTITUTION: A chip part 4 such as an IC chip is mounted on a die bonding pad 2 on a multilayer interconnection substrate 1 through epoxy group adhesives 3 while the chip part 4 and wire bonding pads 5 on the multilayer interconnection substrate 1 are bonded by wires 6 in gold, etc. Electric function inspection is conducted, bias is applied in order to generate initial defectives in the chip parts, the chip parts are aged through heating for approximately 96W240hr at a temperature such as 100W125°C in a clean oven, initial defective chip parts are discovered through electric function inspection, and the parts are repaired or exchanged. The chip parts are hermetically sealed according to a conventional procedure. n COPYRIGHT: (C)1987,JPO&Japio
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111130536-B
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Total number of triples: 22.