http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S61294868-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0a6a69da5879eb83f56f6876dba3e3cf |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 1985-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_454c1a286ca121675896ed46ff19e9c8 |
| publicationDate | 1986-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S61294868-A |
| titleOfInvention | Semiconductor device |
| abstract | PURPOSE: To reduce the resistance value of an N - layer, by forming a low-concentration impurity diffused layer having a reverse conducting type with respect to a semiconductor substrate at a lower part of a side wall on one side, and forming a high- concentration impurity diffused layer having the same impurity as that in the low- concentration diffused layer at a lower part of a side wall on the source side. n CONSTITUTION: On a P-type 100 substrate 1, a gate oxide film 2 is formed. A polysilicon film is formed. Phosphorus is doped by thermal diffusion. Then, with a photoresist film 7 as a mask, anisotropic etching is performed. Thus a gate electrode 3, whose side surface is approximately vertical is formed. With the gate electrode 3 as a mask, phosphorus is implanted in the silicon substrate at a slant angle of about 10° to the drain side. The phosphorus-ion implanted layer is formed so that the layer is separated from the end part of the gate electrode. An oxide film 4' is formed by a plasma CVD method. Thereafter, anisotropic etching is performed until the surface of the silicon substrate 1 is exposed, and a side wall 4 is formed. Arsenic is implanted at a slant angle of about 10° to the source side, which is opposite with respect to the phosphorus-ion implanting direction. Thus, the arsenic-ion implanted layer is formed. Therefore, suppression of a hot carrier effect and the suppression of increase in channel resistance can be simultaneously realized. n COPYRIGHT: (C)1986,JPO&Japio |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0214530-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S63215075-A |
| priorityDate | 1985-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.