http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S61168253-A

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filingDate 1985-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39015748f989933c6cccb85b1d24ec56
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publicationDate 1986-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-S61168253-A
titleOfInvention High withstand voltage mos field effect semiconductor device
abstract PURPOSE:To prevent an erroneous operation in a semiconductor device formed with two MOSFET's of different withstand voltages on the same semiconductor substrate by completely coating a low withstand voltage semiconductor region with semiconductor. CONSTITUTION:In a semiconductor device formed with a high withstand voltage MOSFETB and a low withstand voltage MOSFETC for driving the FETB on the same semiconductor substrate, the pattern of the low withstand voltage FET is completely coated wit aluminum or other semiconductor D. With the thus constructed structure, erroneous operation due to the inversion of the field of the low withstand voltage FET by the influence of the high withstand voltage FET can be prevented.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6617652-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4667756-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0325970-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6989566-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007134728-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6750506-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005251903-A
priorityDate 1985-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 30.