http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S59211235-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-94 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0638 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-314 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate | 1983-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cbb037a216122d09f9f41a880e1f1c27 |
| publicationDate | 1984-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S59211235-A |
| titleOfInvention | Semiconductor device |
| abstract | PURPOSE: To obtain the high-reliability complmentary MOS integrated circuit by forming an arsenic diffusion inhibiting layer between an oxide layer and an arsenic-including layer into which hydrogen can be diffused so as to prevent diffusion of As into the oxide layer. n CONSTITUTION: An Si oxide layer 1, an arsenic diffusion preventing layer 11, an arsenic silicate glass layer 2 and a plasma-CVD-type Si nitride layer 3 are laminated on a semiconductor substrate 5 and an insular region 6 to form a field insulating layer 12. For the arsenic diffusion preventing layer 11, plasma-CVD- type Si nitride, CVD Si nitride or the like in each of which a diffusion coefficient of As is small are used. When annealing the arsenic silicate glass layer 2, As is not diffused into the side of the Si oxide layer 1 by interposition of the preventing layer 11. Because an As transition layer is not formed, generation of positive charge does not occur in spite of hydrogen in the Si nitride layer 3 generated by plasma CVD. Accordingly, a surface level of the semiconductor substrate becomes stable and increase of a leakage current of variation of a threshold voltage can be prevented. n COPYRIGHT: (C)1984,JPO&Japio |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S61288430-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0495991-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S60246642-A |
| priorityDate | 1983-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.