http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S56147483-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_44f82521bd7b49adba4be2e3e4f3b66a
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
filingDate 1980-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a4ed49a5477ea91f30293c20917704b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ab9ffd44c76831f7ab0835556544958
publicationDate 1981-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-S56147483-A
titleOfInvention Manufacture of semiconductor device
abstract PURPOSE:To prevent abnormal leak and alloy spikes in a P-N junction between a diffused layer and substrate by enclosing roughness on the part of the substrate surface, to which an electrode is directly contacted, in a deep diffused region. CONSTITUTION:A field oxide film 2 is formed on a P type Si substrate. A hole is perforated in a gate oxide film 3, and P added poly Si patterns 6 and 6' are formed with a resistmask 5. Etching is performed by CCl4 gas plasma, and roughness 7 is formed on the substrate surface. Then, PSG 8 is applied, heat treatment is performed at a high temperature, a deep N layer 9 is formed, the roughness 7 is enclosed, and an N layer 10 is formed at the same time. The PSG is etched out, As ions are implanted, heat treatment is performed, and an N type source and drain 11 are formed. Finally, PSG is applied, and the electrode is attached. In this constitution, abnormal leak is not generated in the junction between the N layer 9 and the substrate 1, and also the alloy spikes are not generated therein.
priorityDate 1980-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 17.