http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S5586145-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13099 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01019 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01024 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-1147 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-94 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate | 1978-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f57749bf6fa3e2b6a04b8570b7f3a54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c64f26cc48ba783890eecdbb167cf743 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd720699d942c65139f07fdacf1887ee |
| publicationDate | 1980-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S5586145-A |
| titleOfInvention | Manufacture of capacitor |
| abstract | PURPOSE: To plate securely an upper electrode formed over a lower electrode by removing an overhang part formed around the lower electrode when manufacturing a capacitor. n CONSTITUTION: On a semiconductor substrate 1, a multi-layer metallizing layer 2 consisting of chromium, platinum and gold from the bottom is coated, and on the layer, a resist layer 3 with a hole 4 is provided, and making the layer 2 negative, the layer is plated selectively and lower electrode 5 of gold thicker than the layer 3 is formed. At this time, on the rim of the hole 4, an unnecessary brim 5' is formed. Therefore, on the layer 5, a resist layer 10 of a size corresponding to the hole 4 is formed again and the brim 5' is removed by etching with the mixed liquid of potassium iodide. After that, the layer 3 is removed, and on the whole surface including the layer 5 whose side face is exposed too, a chromium layer 6 is coated, then the layer surface is covered with a dielectric silica film 7 and a Cr-Pt-Au metallizing layer 8, and providing a resist layer 11 on both sides, an upper electrode 12 is formed by plating using the layer 8 as a negative electrode. Next, the layer 11 and the unnecessary parts of the layers 7 and 8 are removed. n COPYRIGHT: (C)1980,JPO&Japio |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5404265-A |
| priorityDate | 1978-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.