http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H11354795-A

Outgoing Links

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
filingDate 1999-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7757943d4f35e861b4664c9cf8db808c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fae83565c45559c046ba1398a9c70c9a
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publicationDate 1999-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H11354795-A
titleOfInvention Semiconductor device
abstract (57) Abstract: To suppress an increase in on-resistance due to an increase in resistance of a source layer. A p-type base layer is formed on an n − -type epitaxial layer, and the p-type base layer is formed. An n + type source layer 4 is formed therein. Then, a U-groove 50 reaching the n − -type epitaxial layer 2 from the surface is formed, and a gate oxide film 8 and a gate electrode 9 are formed on the U-groove 50. At this time, The gate oxide film 8 is composed of a uniform thin film portion λ formed on the U-groove side and a thick film portion formed thicker than the thin film portion λ, and the gate electrode 9 formed thereon is U groove 5 0 to the thin film portion λ and the thick film portion.
priorityDate 1999-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 19.