| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-2602
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5006 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 |
| filingDate |
1998-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d811023591eea4a9e0831caffacf61dc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_348a6dffc3073ba87790f13b21852a14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e4733f4aebf3ab14a980ef394e1bd38 |
| publicationDate |
1999-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H11316264-A |
| titleOfInvention |
Parallel test circuit for semiconductor devices |
| abstract |
(57) Abstract: In a parallel test mode, a leakage current capable of generating a data input pad other than a data input pad to which write data is typically applied is detected in a same test stage. Accordingly, a parallel test circuit for a semiconductor memory device that can reduce test time and cost is provided. SOLUTION: In a parallel test circuit of a semiconductor device, A plurality of data input pads, each of which is connected to the data input pads and receives a chip select signal during a normal operation, A plurality of data input buffers for receiving data applied through each data input pad, and switching means for electrically connecting all the data input pads according to a leakage test activation signal applied in a parallel test mode; And |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008065862-A |
| priorityDate |
1997-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |