| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-3202 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31715
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318505
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318572
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318511
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318533
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate |
1998-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a80d6a9d8c490ac9f2fe550425bf7876 |
| publicationDate |
1999-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H1130652-A |
| titleOfInvention |
Semiconductor body having integrated circuit and test method for output circuit of integrated circuit |
| abstract |
PROBLEM TO BE SOLVED: To perform a scan test of a circuit in a short time while testing peripheral circuits of an integrated circuit die on a wafer without physically contacting a bond pad of the die, and a circuit to be tested. Reduce the generation of heat in the interior. The tester includes a scan interface for controlling a scan operation, a signal generator for generating a test signal, a voltmeter, and a second terminal for connecting a TSA terminal or a TSB terminal of the tester to the voltmeter or the signal generator. 1 switching circuit SW 1 and a second switching circuit S connecting the TSC terminal of the tester via a known resistor R to a programmable voltage source Vp. W2 and a test control computer that controls the overall operation of the tester. The peripheral circuits of the integrated circuit die on the wafer, the output buffer 350, the input buffer 360, the electrostatic discharge protection circuit ESD and the bus holder BH are tested without physical contact with the die bond pads. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009075507-A |
| priorityDate |
1997-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |