| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_34263a1d9767236ba10183da556a136b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06 |
| filingDate |
1998-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8956722cc71f51bedee364e874e9ff6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bef1b0de86be9bf084628524c2791caf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08c47ee63be646e093ddc5a542cca2b7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0075e0b68f6b7d1392b503c6a845c0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd25cf75176c3971fcaa0f605efb72f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38d70a76d22f2bbf1a88c7b58588ec7d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96dfd45f76ee77fa0ed53f8f2eeb39f3 |
| publicationDate |
1999-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H11288410-A |
| titleOfInvention |
Microcomputer |
| abstract |
(57) [Summary] [PROBLEMS] To provide a microcomputer having a built-in flash memory which is easy to use. A CPU is a central processing unit, and FMRY is an electrically erasable / writable nonvolatile flash memory. An input terminal Pmode of an operation mode signal MODE for selectively designating a first operation mode in which rewriting of the flash memory FMRY is controlled by the built-in central processing unit CPU and a second operation mode in which an external PROM writer is controlled is provided. . The flash memory FMRY has a large memory block LMB and a small memory block SMB having different storage capacities as units that can be erased in a batch. The small memory block is smaller than the storage capacity of the RAM. The memory blocks LMB and SMB are used according to the amount of information to be stored. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010015265-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012234607-A |
| priorityDate |
1998-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |