http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H11250681-A

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
filingDate 1998-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1ed1a12a9cad7eec448403f74e84394
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31401e3168d4ae5437ad688948fb911c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6409a5e15ec043eca28680ffc7f17ba
publicationDate 1999-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H11250681-A
titleOfInvention Semiconductor integrated circuit device and nonvolatile semiconductor memory erase verify method
abstract PROBLEM TO BE SOLVED: To measure a threshold voltage of a memory cell after emitting electrons without using a negative power supply and to provide a sense amplifier circuit even when measuring a negative threshold voltage. To determine the value of data accurately. SOLUTION: A memory cell array 1 formed in a P-type well 42 and a P-type well 42 are supplied with 0 V and a positive bias potential. A P-type well bias circuit 2 for biasing any one of VNCPAD1, a source line bias circuit 6 for biasing the source region of the memory cell to 0V and a positive bias potential VNCPAD1, a sensed read data, The sense amplifier circuit 13 for amplifying the sensed data, and the P-type well 42 and the source region are each connected to a positive bias potential VNCP. In this mode, data is read by biasing AD1 and using the gate of the memory cell as the read potential. And a VSAN supply circuit 15 for setting the source potential of the VSAN from 0 V to a positive bias potential VNCPAD1.
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priorityDate 1998-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 44.