http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H11242897-A

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
filingDate 1998-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9ba3ea2ca617353bb5e8f843143c8a6
publicationDate 1999-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H11242897-A
titleOfInvention Semiconductor memory integrated circuit device
abstract (57) [Summary] [PROBLEMS] By arranging a redundancy fuse circuit at a position where the wiring length between the redundancy fuse circuit and the redundancy cell array is minimized, the redundancy access does not limit the address access and further reduces the chip area. Plan. SOLUTION: Redundant cell arrays 30 to 32 are arranged on a plurality of memory cell arrays 20 to 23, and corresponding redundancy fuse circuits 80 to 82 are arranged in parallel with the redundant cell arrays. When a defective address is selected, the redundancy judgment signal RDN stops all the sense amplifier controllers 40 to 44. The redundancy signal RED1 selects the redundancy word driver 51 and the sense amplifier controllers 41 and 42 and once RDN Sense amplifier controllers 41 and 42 stopped by Is operated to select the redundancy cell array 30.
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priorityDate 1998-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 20.