http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H11238397-A

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filingDate 1998-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c944aaa4e03eb832598c94b297ed71dd
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publicationDate 1999-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H11238397-A
titleOfInvention Burn-in control circuit for semiconductor memory device
abstract (57) [Problem] To provide a semiconductor memory device having a burn-in control circuit with improved reliability. SOLUTION: A burn-in control circuit 140 according to the present invention receives a signal ΦWBE indicating a burn-in test operation and a 2-bit external address signal (A2 and A3) to generate a control signal ΦNWEn. Signal .PHI.WBE is an active high signal that is deactivated during normal operation and activated during burn-in operation. Here, the signal ΦNWEn is a signal for selectively addressing even / odd lines in the main word line MWLi.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001143497-A
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priorityDate 1997-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.