http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H11175339-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30036 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30189 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3824 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3853 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-318 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 |
| filingDate | 1997-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a00f5c85df56ef9069eb7d043d73b026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8a7f1e7e13fa7a755ea43c8b53d2ee7 |
| publicationDate | 1999-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H11175339-A |
| titleOfInvention | Microcomputer |
| abstract | (57) [Summary] [PROBLEMS] A normal single operation operation and SIMD (Single I The source data required for the operation is supplied without delay while maintaining the consistency of the instruction system with the parallel operation of the nstruction multiple data type. A microcomputer includes first and second memories to each of which a common address is supplied, a first arithmetic circuit coupled to the first and second memories, and a first and a second memory. A second arithmetic circuit coupled to the second memory is configured on the same semiconductor substrate, and data is supplied from one of the first and second memories to the first arithmetic circuit; The arithmetic operation is performed by one arithmetic circuit, A first operation mode in which the second arithmetic circuit stops operating, supplying data from the first memory to the first arithmetic circuit, and transmitting data from the second memory to the second arithmetic circuit; And a second operation mode in which the first operation circuit and the second operation circuit supply an operation. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012113508-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002123388-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8438366-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2284691-A2 |
| priorityDate | 1997-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 74.