| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2175de8bcadd3c1447a15ba8b57051c6 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1048
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4096 |
| filingDate |
1998-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_59a1380358e0e91ce3ff43a4a1399e40 |
| publicationDate |
1999-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H11162167-A |
| titleOfInvention |
Synchronous semiconductor memory device and method for precharging its data input / output line |
| abstract |
(57) Abstract: A semiconductor memory device having a clock synchronous precharge data input / output line is provided. A first column control signal PRECLK is responsive to an internal clock signal PCLK1 responsive to an external clock signal CLK1. 1, a first precharge control signal PCLKDA1, a second precharge control signal PRECL linked to the first column control signal KA1, and a spare signal generation circuit 203 that generates a second column control signal PCLKDD1 that is linked to the first precharge control signal, and is disabled in response to the first column control signal, and the second A column selection signal generation circuit 205 that generates a column selection signal CSL1 that is enabled in response to the first column control signal; and a column enable signal that is enabled in response to the second precharge control signal. A precharge signal generation circuit 207 for generating the precharge signal IOPRB1 which is disabled in response. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I402843-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007095258-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011501332-A |
| priorityDate |
1997-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |