http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10340248-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be055db3c1a09879df07379ba969e223 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28 |
| filingDate | 1997-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ead067e11a89563d39b0f37721a8900 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b1d5eba50ebffe4b3db025e0969d5c8 |
| publicationDate | 1998-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H10340248-A |
| titleOfInvention | Direct memory access device |
| abstract | (57) [Summary] To speed up direct memory access (DMA) transfer related to data exchange. A device (7) for separating a data transfer bus (6) between a memory (RAM) (4) and a peripheral device (5) into an A bus (61) and a B bus (62) is provided. , Two temporary storage devices 81 and 82 are interposed. DM When the A controller 2 receives the data transfer request from the peripheral device 5, the A controller 2 separates the data transfer bus 6 and controls so that the data exchange is completed in two cycles. In the first cycle, the data read from the RAM 4 to the A bus 61 is stored in the first temporary storage device 81, and the data supplied from the peripheral device 5 to the B bus 62 is stored in the second temporary storage device 82. Remember. In the second cycle, the data read from the first temporary storage device 81 to the B bus 62 is received by the peripheral device 5, and the data read from the second temporary storage device 82 to the A bus 61 is written to the RAM 4. . |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-1307569-C |
| priorityDate | 1997-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.