| abstract |
(57) [Summary] To reduce the capacity of a frame memory. A clock pulse generation circuit counts a clock pulse and a system time clock. A counter 40 outputting as A and a clock pulse CL Synchronization pulse generation circuits 391A, 393, and 394 that generate a synchronization pulse ESYNC of a frame period based on K PTS / ADR table register 36 in which presentation time stamp PTS is temporarily stored in correspondence with read start address ADRv from frame memory. And a comparison circuit 38A that detects that the STCA matches the PTS read from the table register 36, and in response to the synchronization pulse ESYNC, causes the PTS and ADR corresponding to the image reproduction order to be read from the table register 36, When the time Δ from the detection of the coincidence to the generation of the synchronization pulse, or the time ｛(frame period) −Δ｝ And a control circuit 37C for loading S into the counter 40. |