http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10214808-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B24B37-10
filingDate 1997-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6b53c47200b827d6e5b29d55d4e70b8
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publicationDate 1998-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H10214808-A
titleOfInvention Polishing method for semiconductor substrate
abstract PROBLEM TO BE SOLVED: To provide a method of polishing a semiconductor substrate used in a process of manufacturing a semiconductor chip, stabilize a polishing rate during polishing and realize selective polishing, and perform CMP of an interlayer insulating film. Thus, it is possible to realize stable end point management with time and end point management using a hard-to-polish layer as a stopper based on selective polishing. SOLUTION: The rotational torque value of a carrier holding a semiconductor substrate and / or its motor current consumption value is monitored. Then, polishing is performed while controlling the rotation speed of the carrier so that the value falls within a range of 50% or less (1.5 times the minimum value) from the minimum value. Polishing utilizing the characteristic that the temperature rise during polishing is suppressed and the fluctuation of the polishing rate is reduced, and in a system where a generated layer in which the polishing rate sharply decreases during polishing is formed, this generated layer is stably present. Method.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007152499-A
priorityDate 1997-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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