http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10199285-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C27-02 |
| filingDate | 1996-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9e6cd1851bcb2201febea2cada0e047b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2abfcd7ecb100a097cd965570c6098a2 |
| publicationDate | 1998-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H10199285-A |
| titleOfInvention | Sample hold circuit |
| abstract | [PROBLEMS] To provide a sample-and-hold circuit that can suppress a leakage of an input signal to an output signal via a parasitic capacitance in a holding mode and always output a stable potential without impairing high-speed performance. The purpose is to: SOLUTION: Voltage superimposing means R3 and R4 supply a first fixed voltage at which a seventh transistor Q8 of a first conductivity type is cut off in a sampling mode, and a first emitter common differential transistor pair Q3 and Q in a holding mode. The second fixed voltage at which the base-emitter voltage of No. 4 is biased in the reverse bias direction is set by switching with the collector current of the third pair of emitter common third differential transistors Q10 and Q11, respectively. |
| priorityDate | 1996-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 |
Total number of triples: 13.