http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10172295-A

Outgoing Links

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
filingDate 1997-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c819bb8880ea6c5083ef479f102dea77
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1522b38bc7cd21ac9cd7db099826a88c
publicationDate 1998-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H10172295-A
titleOfInvention Semiconductor memory device having redundant cell array
abstract (57) Abstract: A semiconductor memory device capable of effectively utilizing redundant memory cells is provided. SOLUTION: An n-bit row address is inputted from the outside and 2 A normal memory cell array including a large number of memory cells designated by n word lines and a large number of bit lines, and a memory cell having a defect in the manufacturing process among the normal memory cells. A row coded by an n-bit defective row address and including a number of n-bit address fuses for outputting a signal that becomes active when the externally applied row address matches the coded defective address. A redundant fuse decoder, and a redundant memory cell array including a plurality of memory cells each designated by a word line and a plurality of bit lines driven by an output of the n-bit address fuse unit.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100549942-B1
priorityDate 1996-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 20.