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filingDate 1997-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93845a2364c244cefc98120dba7ede03
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publicationDate 1998-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H10124203-A
titleOfInvention Method and system for reducing power consumption in electronic circuits
abstract (57) Abstract: Provided are a method and a system in which an electronic circuit consumes less power than a conventional technology. SOLUTION: While the load circuit is operating in a first power mode, up to N data bits are loaded from a memory per cycle of the load circuit, where N is an integer of N> 1. . While the load circuit is operating in the second power mode, up to M data bits are loaded from memory per cycle of the load circuit, where M is an integer of N>M> 0.
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