http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10123223-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2175de8bcadd3c1447a15ba8b57051c6 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2884 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-28 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22 |
| filingDate | 1997-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7afc3d7d78d71568ed35d663943747e0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb7da4eb4e53f40aaf83cd18819a288f |
| publicationDate | 1998-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H10123223-A |
| titleOfInvention | Clock generation method and circuit for test of integrated circuit |
| abstract | (57) [PROBLEMS] To provide an integrated circuit test clock generating method and circuit capable of generating a clock suitable for an integrated circuit test. When a normal operation of an integrated circuit including a JTAG boundary scan test circuit is tested, a JTAG clock for a JTAG boundary scan is input to a test clock input pin TCK of the integrated circuit, and the JTAG clock is input. A test clock for a non-boundary scan test of the integrated circuit 110 is generated by the test clock generator 160 from the clock, and the test of the integrated circuit 110 is performed using the test clock. |
| priorityDate | 1996-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.