http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H10107147-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50
filingDate 1996-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_88308402e518ef16183482f75053b0f9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f8f203a5d00d2943ee0f7612f7981a0a
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publicationDate 1998-04-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H10107147-A
titleOfInvention Semiconductor design method and semiconductor design device
abstract (57) Abstract: In extracting a mask layout parameter of a semiconductor, a resistance value of a diffusion region is extracted with high accuracy. SOLUTION: A MOS transistor and a diffusion region are comprehensively processed as constituent elements of a MOS transistor, and a diffusion resistance is extracted in consideration of the shape of the diffusion region and contact information. Thereby, R1, R of the MOS transistor 1 2 and the rectangular condition of R3 and R4 of the MOS transistor 2 are distinguished, and an accurate resistance value is calculated.
priorityDate 1996-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 20.