http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09509284-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-4016 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-405 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7841 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-405 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate | 1994-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1997-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H09509284-A |
| titleOfInvention | Capacitorless DRAM device on silicon-on-insulator substrate |
| abstract | (57) [Summary] A DRAM has a first semiconductor region (18) of a certain conductivity type on a silicon film of a silicon-on-insulator substrate (22). Second (16) and third (14) semiconductor regions of opposite conductivity type are formed in the first semiconductor region (18). A semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed in the second semiconductor region (16) having a higher doping concentration. An insulating layer (11) is formed on the semiconductor surface. A gate electrode (10) is formed on top of the insulating layer (11) and at least partially with the first (18), second (16), third (14), and fourth (12) semiconductor regions. overlapping. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and third (14) semiconductor regions to store information therein. The amount of charge stored in the storage node (24) is determined by the first semiconductor region (12), the second semiconductor region (16), the storage node (24), and the first electrode including the gate electrode (10). It is controlled by a transistor. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6778424-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7696558-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005136191-A |
| priorityDate | 1993-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.