http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09330348-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50
filingDate 1996-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dbf2f44f30408c703e00eda7d3216841
publicationDate 1997-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H09330348-A
titleOfInvention Description processing method
abstract (57) [Abstract] [PROBLEMS] To provide a description processing method for efficiently performing functional simulation and eliminating ambiguity. A description 24 is a description integrated by a conversion means, and its validity is verified by a simulation means. The expression “tmp1 = A + B;” and the expression “tmp2” described in the block expressing the combinational circuit. = B + C; "means a block 22b representing a sequential circuit. The expressions "Y <= tmp1;" and "Z1 <= in a, 22cb tmp1; "and the expression" Z2 <= tmp2; ", respectively. This reduces the number of times of evaluation. Further, in the description 24, the clock signal C Block 22b synchronized with LK1 and CLK2, respectively The expressions are summarized in a, 22cb. This reduces the number of SensitivityLists. The expressions in the blocks 22ba and 22cb are “be Since it is sandwiched between "gin" and "end", it is evaluated in order.
priorityDate 1996-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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