http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09204776-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2175de8bcadd3c1447a15ba8b57051c6 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-13 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 1996-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4abbe824be87e7388d4c7e95f9f73ed |
| publicationDate | 1997-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H09204776-A |
| titleOfInvention | Clock signal generation circuit for data output buffer in synchronous DRAM device |
| abstract | In a clock signal generating circuit for a data output buffer in a synchronous DRAM device, the generation time point of the external clock signal is adaptively varied according to the frequency of the external clock signal, The data output setup time and output hold time should be guaranteed regardless of the frequency. An internal clock generation circuit 21, a phase detector 31, a switching circuit 32, and a control voltage generation circuit 33. And a low-level time tCL of the external clock signal CLK, which is a reference for generating the internal clock signal, and a reference output holding time tCLrefOH for guaranteeing the output hold time tOH, are compared with each other, and a positive edge of the external clock signal CLK is obtained. The internal clock signal CLKDQ is generated based on one of the negative edge and the negative edge. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9967789-A1 |
| priorityDate | 1995-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.