http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H09115297-A

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filingDate 1995-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 1997-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H09115297-A
titleOfInvention Semiconductor memory integrated circuit device
abstract (57) 【Abstract】 PROBLEM TO BE SOLVED: By arranging a redundancy fuse circuit at a position where the wiring length between a redundancy fuse circuit and a redundancy cell array is minimized, redundancy access does not limit address access, and further the chip area is reduced. Plan. SOLUTION: Redundancy cell arrays 30 to 32 are arranged on a plurality of memory cell arrays 20 to 23, and corresponding redundancy fuse circuits 80 to 82 are arranged in parallel with the redundancy cell array. When the defective address is selected, the redundancy judgment signal RDN stops all the sense amplifier controllers 40 to 44. The redundancy signal RED1 selects the redundancy word driver 51 and the sense amplifier controllers 41 and 42, and once selects RDN. Sense amplifier controller 41, 42 stopped by Are operated to select the redundancy cell array 30.
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Total number of triples: 23.