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publicationDate 1997-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H09114794-A
titleOfInvention Transaction Activation Processor Controlling Memory Transaction Execution in Packet-Switched Cache Coherent Multiprocessor System
abstract (57) Abstract: A multiprocessor computer system having a main memory coupled to a system controller and a plurality of cache coherent subsystems. A system controller activates each memory transaction request when it meets a predetermined activation criterion and blocks each said request until it matches the predetermined criterion. The transaction activation logic compares each memory access request with active transaction state data for all activated memory access requests to detect if activation of a particular memory access request violates a predetermined criteria. An input operation that accesses a data block that is pending and maps to the same cache line as the previously activated operation is Blocked until the pending operation that maps to the same cache line is complete.
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