http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H08504514-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2360-121 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-399 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-363 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-395 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-006 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-399 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-395 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-39 |
| filingDate | 1993-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1996-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H08504514-A |
| titleOfInvention | Video processing hardware |
| abstract | (57) [Summary] The video processing system adds a programmable logic device between the conventional frame buffer (3802) and the conventional digital-analog converter (3811) to provide real-time and off-screen processing capability. Donate to increase the video output capability. The system may have a history FIFO (3805) connected to feed the preceding line to the programmable logic device (3809), so that it is required by the state of the immediately adjacent vertical pixel. Allows operation on the current line changed to. The system may have an input for multiple video sources and an input FIFO for random access by the input stream portion. Another form of the system has a crossbar switch (3905) and multiple memory devices (3906) to allow switching between several possible frame buffer devices. One or more processing units can be added to operate the memory, which is the inactive frame buffer. The processing unit may comprise a programmable logic device (3911) and means for programming the programmable logic device (3901A). |
| priorityDate | 1992-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.