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filingDate 1995-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d64947e17dc5e706ec0111cf29c601f
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publicationDate 1996-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H08265715-A
titleOfInvention Data broadcasting receiver
abstract (57) [Summary] (Correction) [Purpose] To provide a data broadcast receiving device capable of error checking without imposing a heavy burden on the CPU. [Structure] A bitstream signal input from the BS tuner is converted into a packet-unit data signal and then separated into prefix data and data group data. At this time, the error detection circuit detects the presence or absence of an error in the data group data. The error flag is inserted in the prefix data and stored in the prefix memory and the data memory. When each of this data stored in the prefix memory and the data memory is transferred to the memory circuit used in the video game machine, The R loop 483 performs an OR operation on the error flags read from the prefix memory in the time axis direction, and stores the result in the D-FF 486. The CPU refers to the stored OR operation result and confirms whether or not there is an error in the data group data to be transferred.
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Total number of triples: 29.