http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0817924-A

Outgoing Links

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 1994-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_abb18267de8d0ec051743e91ff5649ad
publicationDate 1996-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0817924-A
titleOfInvention Multilayer wiring forming method and multilayer wiring structure
abstract (57) [Abstract] [PROBLEMS] To provide a multilayer wiring forming method and a structure for introducing a misalignment margin at the time of opening a connection hole without providing an overlapping portion on a lower layer wiring in an interlayer connection of the multilayer wiring. [Structure] After forming a first pattern by etching a part of the lower layer wiring 3 in the thickness direction, a sublimable side wall 9 made of a sulfur-based material is formed on a side surface of the mask 8 and the first pattern. The remaining portion in the thickness direction is etched to form a second pattern. The terrace portion 3T of the second pattern serves as a misalignment margin when the connection hole is opened. [Effect] Even if the alignment of the connection hole is deviated, the terrace portion T serves as an etching topper, and the insulating layer 2 is not damaged. Since the width of the terrace portion 3T is determined by self-alignment, the process is stable and the wiring density is highly integrated.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100436773-B1
priorityDate 1994-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 21.