http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H07307090-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
filingDate 1994-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_725a10438754ffe9a61183033e7b2389
publicationDate 1995-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H07307090-A
titleOfInvention Semiconductor memory device
abstract (57) [Summary] [Purpose] To provide a synchronous semiconductor memory device by a new pipeline system which can cope with a high-speed cycle when used in combination with a plurality of access paths. [Structure] A synchronous DRAM that performs internal control in synchronization with a system clock signal, and has two access paths that can operate independently of each other with respect to one memory array M-ARY. (S), (F) Of the column address decoder C-ADCR, the column address latch circuit C-ALAT, the data write amplifier DWAMP, the data read amplifier DRAMP, and the data latch circuit DLAT. Further, a column address buffer C-ADB, a data multiplexer DMPX, a data input buffer DIB, a data output buffer DOB, a control circuit / timing generation circuit CONT / TG, a row address decoder R-ADC. It is composed of a row processing circuit corresponding to R.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5764584-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012178218-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6552959-B2
priorityDate 1994-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 26.