http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0730407-A

Outgoing Links

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filingDate 1991-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c722ee21826d46281c5f0884a9f60d3
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publicationDate 1995-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0730407-A
titleOfInvention Register file with programmable control, decoding and / or data manipulation
abstract (57) [Summary] (Modified) [Purpose] A programmable logic device having a novel architecture is provided. A plurality of control input signals 201 are applied to a programmable mapping array 290 to generate control functions for data path gating, latching or modification. Programmable control features give designers flexibility while the fixed datapath logic is independent of the programmable array. The logic array and datapath logic 280 are formed on the same integrated circuit, thus eliminating the need for I / O buffers that would be required if the device were configured with discrete components. Therefore, the performance of the device is improved. Since the data path does not extend through the array, its performance is not affected by programmability. If desired, the programmable array can be formed with mask programmable devices, fuse-type programmable devices, and the like.
priorityDate 1990-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.