http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0728775-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06 |
| filingDate | 1993-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4fbfa71887ee9c6e432169f95d7f98e2 |
| publicationDate | 1995-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H0728775-A |
| titleOfInvention | Microprocessor |
| abstract | (57) [Summary] (Modified) [Purpose] To provide a microprocessor configured to further delay the sampling time of the READY input signal. In a microprocessor 1 which includes a CPU 2, a bus cycle control unit 3 and a clock generator 5 and samples an input READY signal 30 to control the presence / absence of extension of a bus cycle, a clock generator 5 uses a reference clock 35 and n. AND gates 9 to 12 which generate a clock having a doubled frequency, the bus cycle control unit 3 inputs the reference clock 35 and the n-fold clock, and a READY signal 30. Is provided as a data input, and the outputs of the AND gates 9 to 12 are input to the latch means 7 and 8 as sampling clocks. |
| priorityDate | 1993-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.