http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H07249699-A

Outgoing Links

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filingDate 1994-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d1e4231d41f31410bf259caeec1a95c
publicationDate 1995-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H07249699-A
titleOfInvention Semiconductor integrated circuit device and manufacturing method thereof
abstract (57) [Summary] [Construction] A field oxide film formed by a selective oxidation method and a first buried diffusion layer 10 and a second buried diffusion layer 1 which are shared by a plurality of transistors and also used as wirings. 2. A semiconductor integrated circuit device having a gate electrode line 7 intersecting with the gate electrode line 7 and impurity-implanted regions 14 of the same conductivity type as the well substrate 4 and having a high concentration at both ends in the channel width direction of the gate electrode line 7. The manufacturing method. [Effect] The same conductivity type as that of the well substrate and high concentration is provided in the region where the bird's beaks growing during the gate side surface oxidation process are formed at both ends of the gate electrode line in the channel width direction forming the channel region. By implanting impurities to reduce variations in the gate oxide film thickness of the channel, a highly reliable MOS transistor having a stable threshold value is provided.
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priorityDate 1994-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 23.