http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H07183449-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-50 |
| filingDate | 1993-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d5e017f3c2b8939462c6b0f11c157db |
| publicationDate | 1995-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H07183449-A |
| titleOfInvention | Semiconductor device |
| abstract | (57) [Abstract] [PROBLEMS] To provide a package structure for protecting a MOS integrated circuit from electrostatic stress in a carrying process after packaging of the MOS integrated circuit and a carrying process at the time of mounting. An input / output lead is electrically connected to at least a power supply lead by a conductive tape or a solder alloy lead wire, or a short lead wire or plate at least a part of which is made of a shape memory alloy. Package structure. [Effect] Static electricity is generated because the input / output leads are short-circuited to the power supply leads in the carrying process after packaging and the carrying process when mounting, where the greatest possibility of the most lethal static stress being applied to the MOS integrated circuit. No damage even when applied. Further, in particular, the structure using the solder alloy / shape memory alloy has an advantage that the short circuit is automatically released at the time of mounting. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108630616-A |
| priorityDate | 1993-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.