http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H07130971-A

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filingDate 1993-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a862377d8eacccb6f82a967ebb68f01
publicationDate 1995-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H07130971-A
titleOfInvention Semiconductor integrated circuit device
abstract (57) [Abstract] [Purpose] In a gate array in which a transistor for logic verification is connected to each basic cell, a reduction in operating speed due to the addition of this transistor is prevented. A cross-check transistor includes a polycrystalline silicon film composed of N + type source / drain regions 9aa and 9ab and a P type channel region, a gate oxide film, It is a top-gate type TFT in which a part of the cross-check input wiring 10b is diverted to the gate electrode 10a. The N + type source / drain region 9aa is a director N which is the output end of the gate array through the contact hole 8. The N + type source / drain region 9ab is connected to the + type diffusion layer 6a, and is connected to the cross check output wiring 13f through the contact hole 12a.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2003121812-A
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priorityDate 1993-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.