http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0695874-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30032 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-315 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 |
| filingDate | 1993-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d15dadce1d63e7ce2c6af001e7f6da40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86fa2840d15f597e298b88cdc4e26fa9 |
| publicationDate | 1994-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H0695874-A |
| titleOfInvention | Digital computer system |
| abstract | (57) [Summary] (Modified) [Purpose] Presenting a device for detecting a storage operand overlap for an SS instruction having the same overlap detection condition as a literary move (MVC) instruction, and what is effective for it. To prove. [Structure] This device has 24 bits or 31 bits Applicable to all ESA / 390 addressing modes, including access register addressing for addressing. 24-bit and 31-bit S / 370 addressing is also treated as a special case of access register addressing. In addition, the device has been extended to support other addressing device modes, and examples are shown that include a 64-bit addressing mode. A fast parallel implementation of this device is also presented. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6976255-B1 |
| priorityDate | 1992-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.