| abstract |
(57) [Abstract] [Purpose] To provide a new massively parallel processor and computer system. [Structure] A parallel array processor for large-scale parallel applications is a low output CM equipped with a DRAM processing mechanism. It is formed by the OS and incorporates the processing elements on a single chip. Eight processors on a single chip, with processing elements coupled to themselves, extensive memory, and I / O, are interconnected by a modified hypercube-based topology. These nodes are then interconnected by a hypercube network topology, a modified hypercube network topology, a ring network topology or an in-ring ring network topology. |