http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H06350102-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5198a2a21392d6cbc0bb4898b3fb3d29 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate | 1993-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_671a11a5ab26ca9df4df11335a261f12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6bcf54da26556f7ee906f32c407f6bd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20d5f2306bdb310a40fe85215f42cd0c |
| publicationDate | 1994-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H06350102-A |
| titleOfInvention | Nonvolatile semiconductor memory device and manufacturing method thereof |
| abstract | (57) [Summary] [Object] To provide a highly integrated non-volatile semiconductor memory device and a manufacturing method thereof with a high yield. [Structure] A vertical transistor in which first and second semiconductor layers (1, 2) of the same conductivity type are stacked with a third semiconductor layer (3) of the opposite conductivity type interposed, and a vertical transistor The floating gate (10) formed in the central part of this vertical transistor with the insulating layer (11) interposed between each semiconductor layer (1,2,3) and the upper part of this floating gate (10). A window (1 4) and a plurality of memory cells (M 11 to M 42 ) are arranged in a plane while using the first semiconductor layer (1) as a common semiconductor layer. Second semiconductor layer of each memory cell (M 11 to M 42 ). (2) is connected to one of the word lines (W1 to W4) extending in the row or column direction, and the word line (W1 The value of the current flowing through one of the word lines (~ W4) is read as the information being held by the memory cell group connected to this word line. According to the manufacturing method of the present invention, the first, second, and third semiconductor layers (1, 2, 3) forming the vertical transistor are formed by epitaxial growth. |
| priorityDate | 1993-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.