http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H06244708-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173
filingDate 1993-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_61cb8eee566c94c3e4a9cf7f49247649
publicationDate 1994-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H06244708-A
titleOfInvention Logic gate circuit and semiconductor integrated circuit using the same
abstract (57) [Abstract] [Purpose] The operation delay time is shortened by reducing the number of stages of logic gates connected in series on the signal propagation path from the input to the output of the logic circuit. The two gates 16 and 17 use positive and negative bipolar signal values as input signals, and output positive and negative bipolar signal values 28 and 29 corresponding to a predetermined logic function based on these input signals. [Effect] Since it is not necessary to insert an inverter for matching logic polarity in the logic circuit, the number of stages of logic gates connected in series can be reduced. In addition, each gate 1 By setting the logic threshold values of 6 and 17 to be equal to each other, signal transmission can be performed differentially with a pair of positive and negative polarities, and the delay time per gate stage can be reduced.
priorityDate 1993-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID3033151
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419499693

Total number of triples: 15.