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filingDate 1993-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5ba945e52ef8c6e9866485813974d6f
publicationDate 1994-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H06223581-A
titleOfInvention Soft error tolerant static random access memory
abstract (57) [Summary] (Modified) [Purpose] SR that is resistant to soft errors due to α-particle collisions and that does not require the addition of capacity to the cell. Provide AM. An SRAM having resistance to soft errors due to emission of α particles has an array of high-density memory cells coupled to word lines 73 and 74 and a bit line pair 68, and has a low power supply voltage (for example, 3. Operates at 3 volts). Charging circuit 5 Reference numeral 5 boosts the voltage supplied to the memory array above the power supply voltage, and has an oscillator 57, a charge pump 56, and a voltage regulator 58. The boosted supply voltage reduces the impact of alpha particles striking the memory array at low power supply voltages. By supplying that voltage to the memory array, soft error immunity can be improved without adding capacitance to each memory cell 52, 54.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007258765-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020064698-A
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priorityDate 1992-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 26.