| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-934 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-321 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
1993-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0eba1b946bea1e44e0605fde8c135aa5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_354d84e172f4e2e8673c89f6b4f8751b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3fcbf39640df929b5ddc09fec90cb74c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_885fec402873c24e44877a65252c1cc6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_181143901551c32b422c774b786c2362 |
| publicationDate |
1994-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H06216378-A |
| titleOfInvention |
Method of manufacturing integrated circuit device |
| abstract |
(57) [Abstract] [Purpose] A manufacturing method for improving the sheet resistance of a gate of an integrated circuit device. The passivation layer 30 is deposited on the integrated circuit device by a conventional manufacturing method using silicidation, and then the insulating layer 32 is deposited. The insulating layer is planarized and further polished to expose the passivation layer above gate 18. The portion of the passivation layer above the gate is removed so that it has little effect on the insulating layer or gate. One or both joints 14, The trench 41 above 16 is formed by removing the insulating layer using the passivation layer as an etch stop, and has little effect on the junction or isolation region 42, and the passivation layer above the junction is not affected. Is removed. The gate may be further silicided, and the opening above the gate and the trench above the junction may be each flatly filled with a low sheet resistance conductive material 38 to form a contact. The contact on the joint may be borderless. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001506807-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001068563-A |
| priorityDate |
1992-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |