http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H06209305-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1bc66a0a99641c512713ae8e57fb6b89 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B1-7073 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04J13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L27-22 |
| filingDate | 1992-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_968d63dd2fac5ca68d90d897a2f1521c |
| publicationDate | 1994-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H06209305-A |
| titleOfInvention | Data demodulator |
| abstract | (57) [Summary] (Corrected) [Purpose] Increasing the sampling frequency for A / D conversion, Do not increase the number of shift register stages in the correlator. [Structure] The received signals input via GATE are multiplied by COSωt and SINωt in multipliers M1 and M2, respectively, and L The output COS and SIN components of PF1 and PF2 are added to the steering gates SG1 and SG4, and CLK and CLK are added to the gates. SG1 to SG4 are controlled by signals S1 to S4 of the control circuit CONT, Outputs SIG1, 4 of SG1, 4 are A / D converter AD1, 2, the outputs CLK1, 2 of SG2, 3 are A / D converted and input to the subtractor SUB. The output signal is compared with a threshold value by the comparison circuit COMP through the absolute value conversion circuit ABS, and the output thereof and the borrow signal from the SUB are input to the CONT to generate each control signal. |
| priorityDate | 1992-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.