| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-005 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate |
1993-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_796ae124f20e09ba528e9cefbffe100a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_009112866d21f8ec4a5f2963922d4e08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b48d0a39dc2637b10a5a1c5d51f47af6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1427f5f20a4f7d178e2d74b87263cb31 |
| publicationDate |
1994-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-H06195261-A |
| titleOfInvention |
Semiconductor memory device, synchronous semiconductor memory device, and image processing system |
| abstract |
(57) [Summary] [Object] To provide a semiconductor memory device which can be used not only in a cache system but also in the field of graphic processing. A semiconductor memory device includes a DRAM portion, an SRAM portion, and a DRAM array (10 included in the DRAM portion. 2) and the SRAM array (10 included in the SRAM part 4) Includes a bidirectional data transfer circuit 106 for inputting / outputting data to / from the outside as well as data transfer to / from. DRA The driving of the M array and the data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by the DRAM control circuit (128). The SRAM control circuit (132) controls the driving of the SRAM array, the data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input / output operation. The address for the DRAM array is the DRAM array buffer 108. And a memory cell selecting address in the SRAM array is applied to the SRAM address buffer (116). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009170002-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9819308-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100352311-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6714477-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6130852-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6430103-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100428194-C |
| priorityDate |
1992-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |