http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0613404-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
filingDate 1992-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_034a853c5ade6aa10b342cd9a47a0ff0
publicationDate 1994-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0613404-A
titleOfInvention Semiconductor device and manufacturing method thereof
abstract (57) [Summary] (Modified) [Purpose] High-performance poly-Si TFT with low-temperature process An element structure and a manufacturing process for manufacturing the same are provided. In an insulated gate semiconductor device, a polycrystalline semiconductor layer 102 including a channel region mainly composed of silicon and doped with impurities such as boron, a gate insulating film 10 3, a gate electrode 104 having a sidewall 105, It has at least a gate electrode, a semiconductor thin film 106 doped with impurities selectively formed on the polycrystalline semiconductor layer, and a metal thin film 108 selectively formed on the thin film. [Effect] Self-aligned TF with offset structure T can be formed at a low temperature, and the resistance of the gate electrode and the source / drain region can be reduced at the same time. As a result, a high performance CMOS type poly-Si TFT can be formed on an inexpensive glass substrate.
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priorityDate 1992-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 34.