http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0535698-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177 |
| filingDate | 1991-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_904b71be22abbd72add267b0c3b0ae15 |
| publicationDate | 1993-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H0535698-A |
| titleOfInvention | Information processing equipment |
| abstract | (57) [Abstract] [Purpose] The present invention provides a CP when a master accesses. In a multi-master system equipped with a bus that stops U, the most main feature is to reduce the number of wirings and the number of chips to be mounted. [Structure] The DMAC 13 has an expansion memory I on an expansion bus 20. Bus controller 17 when accessing / O22 To issue a control right request to the HOLD request arbitration circuit 23. After stopping the CPU 11, the bus controller 19 is used to access the extended memory I / O 22. On the other hand, when the sub CPU 21 obtains the control right, the HOLD request arbitration circuit 23 is passed through the bus controller 19. A control right request is issued to the CPU 11, the CPU 11 is stopped, and the CPU host bus 12 is directly connected. |
| priorityDate | 1991-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 20.