http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H05219005-A

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filingDate 1992-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb9439598e816fdcac74eea68c02512a
publicationDate 1993-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H05219005-A
titleOfInvention Variable data rate channels for digital networks
abstract (57) [Summary] (Modified) [Objective] To solve the problem in the transmission of data packets in which the required bit rate is often changed and the number of channels is often changed. Arrangement Data from different data streams to be transmitted are read into buffers 210a-210b of RAM 203. The ISDN channels are combined into slots and U channels, respectively. The data from the buffer is assembled by the microprocessor 202 into ISDN frames in the frame store 206 and transmitted via the ISDN circuit 200. This control information is held by the controller units 207, 208 and 209 of the slot control RAM 213 and RAM 203, respectively. RAM 213 also receives any "skew" from frame store 204 due to different delays on different ISDN channels from receive buffers 211a through 211a. Used for reading to c.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-8905069-A1
priorityDate 1991-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 22.