http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H05173881-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08
filingDate 1991-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e00a1c5dfd91b73e6a95ecaa92e96d8
publicationDate 1993-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H05173881-A
titleOfInvention Information processing equipment
abstract (57) [Abstract] [Purpose] To improve the address translation efficiency of the full-associative small-capacity high-speed address translation mechanism. [Structure] The entry of the high speed conversion table 2 has a valid V There are a bit, a stack entry number, an MP bit, a virtual page address part, and a physical page address part. In the case of index, the selector 4 responds to the MP bits by the comparators 3, 6 From 1 page or 2 page unit, a virtual page address is selected, and the AND gate 5 notifies a logical product hit signal with V bit. Selector 10 includes couplers 8, 9 to 1 Selects and outputs a physical address of page or page unit. In the case of registration, the existence of the adjacent page of the physical address and the virtual and physical page address is confirmed by the comparators 7, 12 and 13, and the conversion table and the register 14 are confirmed by the comparator 15. Check the entry number of the identifier. AND gate 11 Then, the logical product of each comparator and V bit is calculated and this signal is notified. Change the flag in 2 page units.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2008155849-A1
priorityDate 1991-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 16.